HT46R23 datasheet, HT46R23 circuit, HT46R23 data sheet: HOLTEK – A/D Type 8-Bit MCU,alldatasheet, datasheet, Datasheet search site for Electronic. A/D Type 8-Bit MCU (HT46C23 EOL) The HT46R23/HT46C23 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for . HT46R23 Datasheet PDF Download – 8-Bit OTP Microcontroller, HT46R23 data sheet.

Author: Araramar Vorisar
Country: Poland
Language: English (Spanish)
Genre: Photos
Published (Last): 5 August 2007
Pages: 448
PDF File Size: 17.76 Mb
ePub File Size: 13.56 Mb
ISBN: 708-9-14326-845-9
Downloads: 37226
Price: Free* [*Free Regsitration Required]
Uploader: Taramar

If an instruction changes the program counter, two cycles are required ht46r2 complete the instruction. One instruction cycle consists of four system clock cycles. In this situation chronize external logic. When a control transfer takes place, an additional. The contents of the specified data memory are incremented by 1.

This also changes the status register. Instruction fetching and execution are pipelined in such. Each modulation cycle has 64 PWM input clock period. Holtek reserves the right to alter its products without prior notification. The registers states are summarized in the following table.

The device datashert an external interrupt, an internal The ALU provides the following functions: The TBLH is read only and cannot be restored. Otherwise proceed with the next instruction 1 cycle.

HT46R23 Datasheet(PDF) – Holtek Semiconductor Inc

The destination will be within locations. The system clock for the microcontroller is derived from. The reference voltage is VDD. In the case of counter overflows, the counter is lower-order byte buffer. Once the condition is met, the next instruction, fetched during the current instruction execution, xatasheet discarded and a dummy cycle replaces it to get the proper instruction. The program counter then points to the.


Data in the specified data memory is decremented by 1, leaving the result in the accumulator. PCL dtaasheet a short jump. Some registers remain un- and results in the following This is a 2-cycle instruction. The data memory is divided into two functional groups: The contents of the specified data memory are cleared to 0. Otherwise proceed with the next instruction. Enable or disable LVD function. If read, the clock will be blocked to avoid errors. The WDT and prescaler are cleared.

If it is awakening from an interrupt, two sequences may happen. The system clock is internally divided into four non-overlapping clocks. These are stress ratings only. It is particularly suitable for use in products such as washing datasyeet controllers and home appli- ances.

After the TO and PD flags are ex- amined, the reason for chip reset can be determined. When a control transfer takes place, an additional dummy cycle is required. The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. For the most up-to-date information, please visit our web site at http: Current program counter bits Rev.

Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de- coding and execution takes the next instruction cycle.



This option defines how to clear the WDT by instruction. Writing indirectly result in no operation. I2C is a trademark of Philips Semiconductors. The 0 flag is affected. The lower byte of the program counter PCL is a read- able and writeable register 06H. The information appearing in this Data Sheet is believed to be accurate at the time of publication.

Moving data into the. For output datassheet, instructions.

Receive acknowledge bit When the receiver wants to continue to receive the next data byte, it generates an acknowledge bit TXAK at Rev. The contents of the data memory remain unchanged. Once a wake-up event occurs, it takes tSYS sys- tem clock period to resume normal operation. Data of the specified data memory and the carry flag are rotated 1 bit right.

HT4520, HT46R22, HT46R23

Until dqtasheet the TON, the ters, respectively. At nect a pull-high resistor respectively. If the stack is full, power down flag PDand watchdog time-out flag TO. Moving data into the PCL performs a short jump. The contents of the specified data memory and the carry flag are together rotated 1 bit right.

The contents of the specified data memory and the carry flag are rotated 1 bit left.